OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	12/01/2022 06:13:56 PM	rwxr-xr-x
📄 asm_aix_ppc64.s	420 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 byteorder.go	1.82 KB	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu.go	11.87 KB	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_aix.go	619 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_arm.go	2.11 KB	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_arm64.go	3.53 KB	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_arm64.s	771 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_gc_arm64.go	269 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_gc_s390x.go	687 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_gc_x86.go	541 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_gccgo_arm64.go	315 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_gccgo_s390x.go	1.02 KB	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_gccgo_x86.c	1.07 KB	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_gccgo_x86.go	840 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_linux.go	361 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_linux_arm.go	1.36 KB	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_linux_arm64.go	2.1 KB	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_linux_mips64x.go	522 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_linux_noinit.go	351 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_linux_ppc64x.go	815 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_linux_s390x.go	890 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_loong64.go	260 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_mips64x.go	346 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_mipsx.go	270 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_netbsd_arm64.go	4.26 KB	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_other_arm.go	239 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_other_arm64.go	260 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_other_mips64x.go	299 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_ppc64x.go	384 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_riscv64.go	259 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_s390x.go	4.88 KB	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_s390x.s	1.97 KB	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_wasm.go	454 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_x86.go	4.64 KB	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_x86.s	642 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_zos.go	223 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 cpu_zos_s390x.go	643 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 hwcap_linux.go	1.23 KB	12/01/2022 06:13:01 PM	rw-r--r--
📄 syscall_aix_gccgo.go	746 bytes	12/01/2022 06:13:01 PM	rw-r--r--
📄 syscall_aix_ppc64_gc.go	1011 bytes	12/01/2022 06:13:01 PM	rw-r--r--

Editing: cpu_arm64.go

// Copyright 2019 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

package cpu

import "runtime"

const cacheLineSize = 64

func initOptions() {
	options = []option{
		{Name: "fp", Feature: &ARM64.HasFP},
		{Name: "asimd", Feature: &ARM64.HasASIMD},
		{Name: "evstrm", Feature: &ARM64.HasEVTSTRM},
		{Name: "aes", Feature: &ARM64.HasAES},
		{Name: "fphp", Feature: &ARM64.HasFPHP},
		{Name: "jscvt", Feature: &ARM64.HasJSCVT},
		{Name: "lrcpc", Feature: &ARM64.HasLRCPC},
		{Name: "pmull", Feature: &ARM64.HasPMULL},
		{Name: "sha1", Feature: &ARM64.HasSHA1},
		{Name: "sha2", Feature: &ARM64.HasSHA2},
		{Name: "sha3", Feature: &ARM64.HasSHA3},
		{Name: "sha512", Feature: &ARM64.HasSHA512},
		{Name: "sm3", Feature: &ARM64.HasSM3},
		{Name: "sm4", Feature: &ARM64.HasSM4},
		{Name: "sve", Feature: &ARM64.HasSVE},
		{Name: "crc32", Feature: &ARM64.HasCRC32},
		{Name: "atomics", Feature: &ARM64.HasATOMICS},
		{Name: "asimdhp", Feature: &ARM64.HasASIMDHP},
		{Name: "cpuid", Feature: &ARM64.HasCPUID},
		{Name: "asimrdm", Feature: &ARM64.HasASIMDRDM},
		{Name: "fcma", Feature: &ARM64.HasFCMA},
		{Name: "dcpop", Feature: &ARM64.HasDCPOP},
		{Name: "asimddp", Feature: &ARM64.HasASIMDDP},
		{Name: "asimdfhm", Feature: &ARM64.HasASIMDFHM},
	}
}

func archInit() {
	switch runtime.GOOS {
	case "freebsd":
		readARM64Registers()
	case "linux", "netbsd":
		doinit()
	default:
		// Most platforms don't seem to allow reading these registers.
		//
		// OpenBSD:
		// See https://golang.org/issue/31746
		setMinimalFeatures()
	}
}

// setMinimalFeatures fakes the minimal ARM64 features expected by
// TestARM64minimalFeatures.
func setMinimalFeatures() {
	ARM64.HasASIMD = true
	ARM64.HasFP = true
}

func readARM64Registers() {
	Initialized = true

parseARM64SystemRegisters(getisar0(), getisar1(), getpfr0())
}

func parseARM64SystemRegisters(isar0, isar1, pfr0 uint64) {
	// ID_AA64ISAR0_EL1
	switch extractBits(isar0, 4, 7) {
	case 1:
		ARM64.HasAES = true
	case 2:
		ARM64.HasAES = true
		ARM64.HasPMULL = true
	}

switch extractBits(isar0, 8, 11) {
	case 1:
		ARM64.HasSHA1 = true
	}

switch extractBits(isar0, 12, 15) {
	case 1:
		ARM64.HasSHA2 = true
	case 2:
		ARM64.HasSHA2 = true
		ARM64.HasSHA512 = true
	}

switch extractBits(isar0, 16, 19) {
	case 1:
		ARM64.HasCRC32 = true
	}

switch extractBits(isar0, 20, 23) {
	case 2:
		ARM64.HasATOMICS = true
	}

switch extractBits(isar0, 28, 31) {
	case 1:
		ARM64.HasASIMDRDM = true
	}

switch extractBits(isar0, 32, 35) {
	case 1:
		ARM64.HasSHA3 = true
	}

switch extractBits(isar0, 36, 39) {
	case 1:
		ARM64.HasSM3 = true
	}

switch extractBits(isar0, 40, 43) {
	case 1:
		ARM64.HasSM4 = true
	}

switch extractBits(isar0, 44, 47) {
	case 1:
		ARM64.HasASIMDDP = true
	}

// ID_AA64ISAR1_EL1
	switch extractBits(isar1, 0, 3) {
	case 1:
		ARM64.HasDCPOP = true
	}

switch extractBits(isar1, 12, 15) {
	case 1:
		ARM64.HasJSCVT = true
	}

switch extractBits(isar1, 16, 19) {
	case 1:
		ARM64.HasFCMA = true
	}

switch extractBits(isar1, 20, 23) {
	case 1:
		ARM64.HasLRCPC = true
	}

// ID_AA64PFR0_EL1
	switch extractBits(pfr0, 16, 19) {
	case 0:
		ARM64.HasFP = true
	case 1:
		ARM64.HasFP = true
		ARM64.HasFPHP = true
	}

switch extractBits(pfr0, 20, 23) {
	case 0:
		ARM64.HasASIMD = true
	case 1:
		ARM64.HasASIMD = true
		ARM64.HasASIMDHP = true
	}

switch extractBits(pfr0, 32, 35) {
	case 1:
		ARM64.HasSVE = true
	}
}

func extractBits(data uint64, start, end uint) uint {
	return (uint)(data>>start) & ((1 << (end - start + 1)) - 1)
}